Method and apparatus for skewing data with respect to command on a DDR interface
US7181638B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 12, 2002 |
| Grant date | Feb 20, 2007 |
| Priority date | — |
| Expiry date | Dec 31, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An adjustable logic circuit includes a pulse filter and delay circuit, a state machine and combinational logic circuit, and a data strobe generation circuit. The pulse filter and delay circuit is operative to read an adjustable configuration value and, based thereon, to implement a delay between an internal clock and both a data signal and a data strobe signal, the delay being a fraction of a clock period. The state machine and combinational logic circuit are operative to select a data value from a plurality of data values, and to provide a data signal based upon the data value. The data strobe generation circuit is operative to provide the data strobe signal at a time when both the data signal is valid and the delay is compatible with a predetermined external device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.