Method, system, and apparatus for supporting power loss recovery in ECC enabled memory devices
US7181672B2 · kind B2 · utility
5Cited by
3References
20Claims
0Family size
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Key dates
| Filing date | Sep 25, 2003 |
| Grant date | Feb 20, 2007 |
| Priority date | — |
| Expiry date | Mar 12, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1068
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique for coalesced Power Loss Recovery PLR status bits in an Error Correction Code ECC enabled flash memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.