Prioritizing of nets for coupled noise analysis
US7181711B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 27, 2005 |
| Grant date | Feb 20, 2007 |
| Priority date | — |
| Expiry date | Jun 2, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method of performing microelectronic chip timing analysis, wherein the method comprises identifying failing timing paths in a chip; prioritizing the failing timing paths in the chip according to a size of random noise events occurring in each timing path; attributing a slack credit statistic for all but highest order random noise events occurring in each timing path; and calculating a worst case timing path scenario based on the prioritized failing timing paths and the slack credit statistic. Preferably, the random noise events comprise non-clock events. Moreover, the random noise events may comprise victim/aggressor net groups belonging to different regularity groups. Preferably, the size of random noise events comprises coupled noise delta delays due to the random noise events occurring in the chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.