Eric A. Foreman
91Patents
10h-index
57Co-inventors
77Inventor score
Filing activity: Apr 29, 2004 → Aug 16, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7089143B2 | Method and system for evaluating timing in an integrated circuit | Physics | 25 | Expired |
| US7620921B2 | IC chip at-functional-speed testing with process coverage evaluation | Physics | 23 | Active |
| US7555740B2 | Method and system for evaluating statistical sensitivity credit in path-based hybrid multi-corner static timing analysis | Physics | 20 | Active |
| US7181711B2 | Prioritizing of nets for coupled noise analysis | Physics | 17 | Expired |
| US8839167B1 | Reducing runtime and memory requirements of static timing analysis | Physics | 17 | Active |
| US8141012B2 | Timing closure on multiple selective corners in a single statistical timing run | Physics | 17 | Active |
| US7401307B2 | Slack sensitivity to parameter variation based timing analysis | Physics | 17 | Expired |
| US8719763B1 | Frequency selection with selective voltage binning | Physics | 15 | Active |
| US8413095B1 | Statistical single library including on chip variation for rapid timing and power analysis | Physics | 14 | Active |
| US8856709B2 | Systems and methods for correlated parameters in statistical static timing analysis | Physics | 12 | Active |
| US8141014B2 | System and method for common history pessimism relief during static timing analysis | Physics | 10 | Active |
| US7784003B2 | Estimation of process variation impact of slack in multi-corner path-based static timing analysis | Physics | 10 | Active |
| US9495497B1 | Dynamic voltage frequency scaling | Physics | 9 | Active |
| US9939880B1 | Voltage and frequency balancing at nominal point | Physics | 9 | Active |
| US7716616B2 | Slack sensitivity to parameter variation based timing analysis | Physics | 8 | Active |
| US9269407B1 | System and method for managing circuit performance and power consumption by selectively adjusting supply voltage over time | Physics | 7 | Active |
| US9501609B1 | Selection of corners and/or margins using statistical static timing analysis of an integrated circuit | Physics | 7 | Active |
| US9767239B1 | Timing optimization driven by statistical sensitivites | Physics | 7 | Active |
| US8707233B2 | Systems and methods for correlated parameters in statistical static timing analysis | Physics | 7 | Active |
| US9519747B1 | Dynamic and adaptive timing sensitivity during static timing analysis using look-up table | Physics | 7 | Active |
| US7873926B2 | Methods for practical worst test definition and debug during block based statistical static timing analysis | Physics | 7 | Active |
| US8468483B2 | Method, system and program storage device for performing a parameterized statistical static timing analysis (SSTA) of an integrated circuit taking into account setup and hold margin interdependence | Physics | 7 | Active |
| US7444608B2 | Method and system for evaluating timing in an integrated circuit | Physics | 7 | Active |
| US9483604B1 | Variable accuracy parameter modeling in statistical timing | Physics | 6 | Active |
| US10222852B2 | Voltage and frequency balancing at nominal point | Physics | 6 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.