Method of optimizing critical path delay in an integrated circuit design
US7181712B2 · kind B2 · utility
1Cited by
6References
4Claims
0Family size
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Key dates
| Filing date | Oct 27, 2004 |
| Grant date | Feb 20, 2007 |
| Priority date | — |
| Expiry date | Mar 23, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and computer program product for optimizing critical path delay in an integrated circuit design include steps of: (a) receiving as input an integrated circuit design; (b) performing a timing/crosstalk analysis to identify each timing critical net in the integrated circuit design; (c) selecting an optimum interconnect configuration for minimizing path delay in each timing critical net; (e) performing a detailed routing that includes the selected optimum interconnect configuration for each timing critical net; and (f) generating as output the detailed routing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.