Semiconductor device and fabrication method therefor
US7183190B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 27, 2001 |
| Grant date | Feb 27, 2007 |
| Priority date | — |
| Expiry date | Feb 16, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of efficiently and inexpensively fabricating a chip-size package having an electrode pitch expanded by forming a conductor wiring on the electrode forming surface side of a semiconductor chip, especially, a method for facilitating wiring and bump forming. A semiconductor device comprising a semi-conductor elements and conductor wirings formed on the semiconductor elements by etching wiring-forming metal foil; and a fabrication method for a semiconductor device comprising the steps of laminating wiring forming metal foil on the electrode forming surface side on the semiconductor, forming a resist wiring pattern on the metal foil, etching the metal foil, and slicing the device into individual elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.