Method of reducing the pattern effect in the CMP process
US7183199B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 1, 2003 |
| Grant date | Feb 27, 2007 |
| Priority date | — |
| Expiry date | Mar 11, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/7684
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of reducing the pattern effect in the CMP process. The method comprises the steps of providing a semiconductor substrate having a patterned dielectric layer, a barrier layer on the patterned dielectric layer, and a conductive layer on the barrier layer; performing a first CMP process to remove part of the conductive layer before the barrier layer is polished, thereby a step height of the conductive layer is reduced; depositing a layer of material substantially the same as the conductive layer on the conductive layer; and performing a second CMP process to expose the dielectric layer. A method of eliminating the dishing phenomena after a CMP process and a CMP rework method are also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.