Method for fabricating a semiconductor device
US7183200B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 28, 2005 |
| Grant date | Feb 27, 2007 |
| Priority date | — |
| Expiry date | Oct 9, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device has a multi-layer interconnection structure with a first interlayer insulation film and a second interlayer insulation film that is formed on the first interlayer insulation film and has a hardness and an elastic modulus larger than those of the first interlayer insulation film, and is fabricated by a step of forming a resist film on the second interlayer insulation film via an antireflective film, a step of exposing to light and developing the resist film to form a resist pattern, and a step of patterning the antireflective film and the multi-layer interconnection structure using the resist pattern as a mask, wherein a film with no stress or for storing compressive stress is used as the antireflective film.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.