Microelectronic mechanical system and methods
US7183637B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 13, 2005 |
| Grant date | Feb 27, 2007 |
| Priority date | — |
| Expiry date | May 13, 2025 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB81C2203/0735
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
The current invention provides for encapsulated release structures, intermediates thereof and methods for their fabrication. The multi-layer structure has a capping layer, that preferably comprises silicon oxide and/or silicon nitride, and which is formed over an etch resistant substrate. A patterned device layer, preferably comprising silicon nitride, is embedded in a sacrificial material, preferably comprising polysilicon, and is disposed between the etch resistant substrate and the capping layer. Access trenches or holes are formed in to capping layer and the sacrificial material are selectively etched through the access trenches, such that portions of the device layer are release from sacrificial material. The etchant preferably comprises a noble gas fluoride NGF2x (wherein Ng=Xe, Kr or Ar: and where x=1, 2 or 3). After etching that sacrificial material, the access trenches are sealed to encapsulate released portions the device layer between the etch resistant substrate and the capping layer. The current invention is particularly useful for fabricating MEMS devices, multiple cavity devices and devices with multiple release features.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.