Synchronous memory
US7183798B1 · kind B1 · utility
2Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 24, 2005 |
| Grant date | Feb 27, 2007 |
| Priority date | — |
| Expiry date | May 23, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1774
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Systems and methods are disclosed herein to provide improved memory techniques for logic blocks within a programmable logic device. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a first and a second logic slice adapted to receive a first and a second clock signal. The first and second logic slices may be combined to form wider and deeper memory and single port or synchronous dual port memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.