Xiaojie He
24Patents
6h-index
40Co-inventors
69Inventor score
Filing activity: Jun 6, 1999 → Dec 27, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6184713A | Scalable architecture for high density CPLDS having two-level hierarchy of routing resources | Electricity | 193 | Expired |
| US6348813B1 | Scalable architecture for high density CPLD's having two-level hierarchy of routing resources | Electricity | 128 | Expired |
| US7385417B1 | Dual slice architectures for programmable logic devices | Electricity | 43 | Active |
| US6150841A | Enhanced macrocell module for high density CPLD architectures | Electricity | 26 | Expired |
| US8175528B2 | Wireless mass storage flash memory | Electricity | 13 | Active |
| US7685215B1 | Fast-carry arithmetic circuit using a multi-input look-up table | Physics | 6 | Active |
| US7564716B2 | Memory device with retained indicator of read reference level | Physics | 6 | Active |
| US6653860B2 | Enhanced macrocell module having expandable product term sharing capability for use in high density CPLD architectures | Electricity | 5 | Expired |
| US7592834B1 | Logic block control architectures for programmable logic devices | Electricity | 4 | Active |
| US7397276B1 | Logic block control architectures for programmable logic devices | Electricity | 3 | Active |
| US7183798B1 | Synchronous memory | Electricity | 2 | Expired |
| US10775874B2 | Multi-tiered low power states | Emerging Cross-Sectional Technologies | 2 | Active |
| US11460879B1 | System and method for controlling electrical current supply in a multi-processor core system via instruction per cycle reduction | Emerging Cross-Sectional Technologies | 1 | Active |
| US7675321B1 | Dual-slice architectures for programmable logic devices | Electricity | 1 | Active |
| US7696784B1 | Programmable logic device with multiple slice types | Electricity | 1 | Active |
| US7605606B1 | Area efficient routing architectures for programmable logic devices | Electricity | 1 | Active |
| US11567557B2 | Electrical power operating states for core logic in a memory physical layer | Emerging Cross-Sectional Technologies | 0 | Active |
| USD1081109S1 | Needle threader | General | 0 | Active |
| US10712800B2 | Aligning active and idle phases in a mixed workload computing platform | Emerging Cross-Sectional Technologies | 0 | Active |
| USD1057080S1 | Live shrimp hook | General | 0 | Active |
| US11644853B2 | Power delivery system having low- and high-power power supplies | Physics | 0 | Active |
| US7378872B1 | Programmable logic device architecture with multiple slice types | Electricity | 0 | Active |
| US11455025B2 | Power state transitions | Emerging Cross-Sectional Technologies | 0 | Active |
| US11853111B2 | System and method for controlling electrical current supply in a multi-processor core system via instruction per cycle reduction | Emerging Cross-Sectional Technologies | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.