Memory device
US7184296B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 3, 2005 |
| Grant date | Feb 27, 2007 |
| Priority date | — |
| Expiry date | Mar 3, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device has a data line (DATA-BUS) for connection to a memory cell, a reference line (Reference-BUS) for reference, a precharge circuit (101), a load circuit (102), and an amplifier circuit (103). The precharge circuit is connected to the data line and the reference line and configured to precharge the data line and the reference line. The load circuit is connected to the data line and the reference line and configured to apply a first constant current to the data line and apply a second constant current which is smaller than the first constant current to the reference line. The amplification circuit is connected to the data line and the reference line and configured to amplify a differential voltage between the data line and the reference line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.