Flash memory device capable of preventing program disturbance according to partial programming
US7184307B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 5, 2004 |
| Grant date | Feb 27, 2007 |
| Priority date | — |
| Expiry date | Aug 19, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile semiconductor memory device disclosed herein includes arrays of memory cells arranged along rows and columns. The columns are divided into at least two column regions and each row is divided into two electrically isolated word lines that are arranged in the column regions. The memory device further includes a determining circuit for judging which column region a data loaded on a register belongs to during a program operation, and a selecting circuit for choosing one of the rows in response to the row address information and driving one or all of the word lines in the selected row with a program voltage according to the judging.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.