Circuit and method for test mode entry of a semiconductor memory device
US7184340B2 · kind B2 · utility
10Cited by
3References
22Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 21, 2005 |
| Grant date | Feb 27, 2007 |
| Priority date | — |
| Expiry date | Oct 21, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/46
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit and method for test mode entry of a semiconductor memory device are provided. In a method of entering a semiconductor memory device into a test mode, an internal clock is generated in response to an external clock when a first condition is satisfied. An address combination signal is generated based on a first address combination and the internal clock. The semiconductor memory device is entered into the test mode using the internal clock and the address combination signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.