Complementary code decoding by reduced sized circuits

US7184496B2 · kind B2 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Uwe Eckhardt · Dresden, DE
• Eric Sachse · Leipzig, DE
• Ingo Kuhn · Dresden, DE

Key dates

• Filing date: Jun 19, 2003
• Grant date: Feb 27, 2007
• Expiry date: Sep 5, 2025

Classification

• Technology area (CPC H): Electricity
• CPC primary: H04B1/7093
• WIPO field: Telecommunications
• WIPO sector: Electrical engineering

Abstract

A complementary code decoder technique is provided where the encoded input data is first parallelized. From the parallelized data, correlation values are generated by a correlator circuit that is capable of changing its correlation characteristics depending on at least one control signal. Different control signals are sequentially provided to the correlator circuit thereby driving the correlator circuit to sequentially generate multiple correlation values from the parallelized data, based on different correlation characteristics. From the multiple correlation values, the correlation value that represents the optimum correlation is identified. This technique significantly reduces the gate count of the decoder structure, thus saving chip area and manufacturing costs.