Receiver having an integrated clock phase detector
US7184504B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 10, 2002 |
| Grant date | Feb 27, 2007 |
| Priority date | — |
| Expiry date | Sep 12, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0054
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Receiver is provided having an integrated clock phase detector for the detection of the clock phase deviation between desired sampling instants and the sampling instants of a reception signal which is transmitted from a transmitter (2) with a transmission filter via a transmission channel (3) to the receiver (1). The receiver has at least one matched filter (8) and at least one frequency matched filter (9). The magnitude of a first convolution product of the impulse response of the transmission filter, of the transmission channel (3) and of the matched filter (8), for the maximization of the signal/noise power ratio (SNR) of the reception signal, is maximal at the desired sampling instants. The transfer function FMF (f) of the frequency matched filter (9) is the first derivative in the frequency domain of the transfer function ME (f) of the matched filter (8), in which case at least one multiplier (11) is provided, which multiplies an output signal of the matched filter (8) by an output signal of the frequency matched filter (9) to form a clock phase deviation detection signal (TP).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.