Residual phase error correction
US7184507B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2002 |
| Grant date | Feb 27, 2007 |
| Priority date | — |
| Expiry date | Feb 12, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04W84/12
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A phase error correction technique in data communication receivers such as WLAN (Wireless Local Area Network) receivers is provided. A signal having a phase error is received, and a phase error correction mechanism having a loop structure is operated on the input signal to correct the phase error. The corrected signal still has a residual phase error. The residual phase error is then compensated taking into account a loop time delay of the loop structure. Further, a phase change rate may be taken into account, and a smoothing process may additionally be performed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.