Wafer-level testing of optical and optoelectronic chips
US7184626B1 · kind B1 · utility
23Cited by
10References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 7, 2004 |
| Grant date | Feb 27, 2007 |
| Priority date | — |
| Expiry date | Jul 8, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02B6/4224
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
This application describes, among others, wafer designs, testing systems and techniques for wafer-level optical testing by coupling probe light from top of the wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.