Method and apparatus for secure scan testing

US7185249B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Thomas E. Tkacik · Phoenix, US
• John E. Spittal, Jr. · Waddell, US
• Jonathan Lutz · Kitchener, CA
• Lawrence Case · Boynton Beach, US
• Douglas A. Hardy · Scottsdale, US
• Mark D. Redman · Gilbert, US
• Gregory Schmidt · Chandler, US
• Steven Tugeberg · Scottsdale, US
• Michael D. Fitzsimmons · Austin, US
• Darrell L. Carder · Dripping Springs, US

Key dates

• Filing date: Apr 30, 2002
• Grant date: Feb 27, 2007
• Expiry date: Apr 10, 2023

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/318544
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A processor, scan controller, and method for protecting sensitive information from electronic hacking is disclosed. To maintain the security of the sensitive data present in a processor, the scan controller denies access to the scan chain until data is cleared from scan-observable portions of the processor, then clears the scan chain again prior to exiting test mode and resuming normal operation. Clearing or otherwise modifying data stored in the scan-observable portions of a processor when transitioning to and/or from a test mode will prevent unauthorized personnel from simply shifting secure data out of the scan chain, and from pre-loading data into the scan chain prior to normal operation in an attempt to set sensitive state information.