Compacting circuit responses
US7185253B2 · kind B2 · utility
23Cited by
7References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2002 |
| Grant date | Feb 27, 2007 |
| Priority date | — |
| Expiry date | Jun 16, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318547
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Circuit responses to a stimulus may be compacted, decreasing the number of pin outs, without increasing the circuit element length, using a compactor. In accordance with one embodiment of the present invention, errors may be detected in scan chains used for integrated circuit testing. The number of outputs applied to output pins or other connectors may be substantially decreased, resulting in cost savings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.