Method for generating layouts by chamfering corners of polygons
US7185302B1 · kind B1 · utility
0Cited by
1References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2004 |
| Grant date | Feb 27, 2007 |
| Priority date | — |
| Expiry date | Feb 4, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for generating a layout of a semiconductor circuit to satisfy minimum spacing requirements that includes generating one or more polygons for the layout, with each generated polygon having an area, a plurality of corners and satisfying the minimum spacing requirements of the layout rules. The corners of the generated polygon are then chamfered, and the generated polygon with chamfered corners is expanded or reduced in size.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.