Method of manufacturing a semiconductor package
US7185426B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 23, 2004 |
| Grant date | Mar 6, 2007 |
| Priority date | — |
| Expiry date | Dec 13, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49167
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor package including top-surface terminals for mounting another semiconductor package provides a three-dimensional circuit configuration that can provide removable connection of existing grid-array packages having a standard design. A semiconductor die is mounted on an electrically connected to a circuit substrate having terminals disposed on a bottom side for connection to an external system. The die and substrate are encapsulated and vias are laser-ablated or otherwise formed through the encapsulation to terminals on the top surface of the substrate that provide a grid array mounting lands to which another grid array semiconductor package may be mounted. The bottom side of the vias may terminate and electrically connect to terminals on the substrate, terminals on the bottom of the semiconductor package (through terminals) or terminals on the top of the semiconductor die. The vias may be plated, paste-filled, filled with a low melting point alloy and may have a conical profile for improved plating performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.