Barrier first method for single damascene trench applications
US7186648B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 18, 2004 |
| Grant date | Mar 6, 2007 |
| Priority date | — |
| Expiry date | Jun 5, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76865
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods for forming a diffusion barrier on low aspect features of an integrated circuit include at least three operations. The first operation deposits a barrier material and simultaneously etches a portion of an underlying metal at the bottoms of recessed features of the integrated circuit. The second operation deposits barrier material to provide some minimal coverage over the bottoms of the recessed features. The third operation deposits a metal conductive layer. Controlled etching is used to selectively remove barrier material from the bottom of the recessed features, either completely or partially, thus reducing the resistance of subsequently formed metal interconnects.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.