High-density metal capacitor using dual-damascene copper interconnect
US7187015B2 · kind B2 · utility
11Cited by
29References
32Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 22, 2005 |
| Grant date | Mar 6, 2007 |
| Priority date | — |
| Expiry date | Jul 15, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76807
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electronic structure having a first conductive layer provided by a dual damascene fabrication process; an etch-stop layer provided by the fabrication process, and electrically coupled with the first conductive layer, the etch-stop layer having a preselected dielectric constant and a predetermined geometry; and a second conductive layer, electrically coupled with the etch-stop layer. The structure can be, for example, a metal-insulator-metal capacitor, an antifuse, and the like.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.