Device for probe card power bus voltage drop reduction
US7187194B2 · kind B2 · utility
2Cited by
6References
3Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 5, 2005 |
| Grant date | Mar 6, 2007 |
| Priority date | — |
| Expiry date | Oct 5, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31721
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Noise reduction for application of structural test patterns to a Device Under Test (DUT) is accomplished with a capacitor “booster” bypass network on the probe card in which the capacitors are charged to a much higher voltage Vboost than the DUT power supply voltage VDD. Charging the capacitors to a voltage N×VDD allows the buster network to store N times the charge of a conventionally configured capacitance network, and effectively provides N times the capacitance of the original network in the same physical space.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.