Driver circuit
US7187227B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 6, 2003 |
| Grant date | Mar 6, 2007 |
| Priority date | — |
| Expiry date | Jan 21, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/102
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A driver circuit includes first and second three-terminal active elements, and first and second delay units. The first and second three-terminal active elements are series-connected. Each of the first and second three-terminal active elements has an amplification function and first, second, and third electrodes. The second and third electrodes of each three-terminal active element are series-connected between the first and second potentials. The first and second delay units receive the same input signal. The outputs of the first and second delay units are respectively connected to the first electrodes of the first and second three-terminal active elements. The delay amount of the second delay unit is larger than that of the first delay unit. The delay amount of the first delay unit is a finite value including zero.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.