Memory having power-up circuit
US7187612B2 · kind B2 · utility
2Cited by
4References
32Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 29, 2005 |
| Grant date | Mar 6, 2007 |
| Priority date | — |
| Expiry date | Aug 27, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4094
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory includes a power-up circuit configured to increase a first voltage to a first value with a second voltage tied to ground, reduce the first voltage from the first value to a second value with the second voltage floating to reduce the second voltage through a parasitic coupling capacitance, and pump the second voltage to reduce the second voltage to a third value with the first voltage less than the second value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.