Boundary scan analysis
US7188043B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 30, 2004 |
| Grant date | Mar 6, 2007 |
| Priority date | — |
| Expiry date | Jan 30, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318544
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A circuit testing approach involves the generation of boundary scan information using test vectors to identify characteristics of a circuit design and a boundary scan implementation therefor. According to an example embodiment of the present invention, test vectors are used in simulation to identify circuit design characteristics for establishing a boundary scan test program. The test vectors are generated using a netlist of the circuit design. The test vectors are used to simulate operation of the circuit, and responses to the simulation are detected and used to identify design-specific circuit characteristics and a boundary scan test program is generated using the design-specific circuit characteristics.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.