Side-by-side inverted memory address and command buses
US7188208B2 · kind B2 · utility
4Cited by
13References
20Claims
0Family size
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Key dates
| Filing date | Sep 7, 2004 |
| Grant date | Mar 6, 2007 |
| Priority date | — |
| Expiry date | Mar 30, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Generating a pair of buses, each coupled to a common terminating device, each having a set of address signal lines that are coupled to a separate memory device, and driving one set of address signal lines with an address driven with true logic states while driving the other set of address signal lines with the same address, but driven to opposing logic states, to achieve a greater balance between the quantity of signals across both buses that are driven to a high state versus those that are driven to a low state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.