Memory repair analysis method and circuit
US7188274B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 2004 |
| Grant date | Mar 6, 2007 |
| Priority date | — |
| Expiry date | Aug 28, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/72
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and circuit for repairing a memory array having one or more memory segments each having one spare column and a predetermined number of spare rows common to all segments, the method comprises, while testing the memory array for failures, generating an equal number of unique segment repair solutions for each segment with each segment repair solution including one defective column address, if any, and a number of defective row addresses, if any, corresponding to the predetermined number of spare rows; and, after completing testing, analyzing all segment repair solution combinations consisting of one segment repair solution selected from each segment; and identifying the best segment repair solution combination of combinations having a number of different defective row addresses which is less than or equal to the predetermined number of spare rows.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.