ECC for component failures using Galois fields
US7188296B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 30, 2003 |
| Grant date | Mar 6, 2007 |
| Priority date | — |
| Expiry date | Apr 27, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/2909
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus comprises a check bit encoder circuit and a check/correct circuit. The apparatus operates on encoded data blocks, wherein each encoded data block includes a data block, a first plurality of check bits, and a second plurality of check bits. The encoded data block is logically arranged as an array of R rows and N columns, and each of the N columns comprises data bits from a respective one of the plurality of components. The first check bits form a first column of the array, and each of the first check bits covers a row of the array. The second check bits form a second column of the array and are defined to cover bits in the array according to a plurality of check vectors. Each check vector corresponds to a different bit in the array and is an element of a Galois Field (GF(2R)). The check vectors are derived from a plurality of unique elements of GF(2R), each of which corresponds to a different column of the array. The check vector in row X of the column is the product, in GF(2R), of the unique element for that column and alphaX, wherein alpha is a primitive element of GF(2R).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.