Circuit layout methodology using a shape processing application
US7188322B2 · kind B2 · utility
176Cited by
7References
16Claims
0Family size
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Key dates
| Filing date | Feb 25, 2005 |
| Grant date | Mar 6, 2007 |
| Priority date | — |
| Expiry date | May 21, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit layout methology is provided for eliminating the extra processing time and file-space requirements associated with the optical proximity correction (OPC) of a VLSI design. The methodology starts with the design rules for a given manufacturing technology and establishes a new set of layer-specific grid values. A layout obeying these new grid requirements leads to a significant reduction in data preparation time, cost, and file size. A layout-migration tool can be used to modify an existing layout in order to enforce the new grid requirements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.