Manufacturing method for a recessed channel array transistor and corresponding recessed channel array transistor
US7189617B2 · kind B2 · utility
11Cited by
2References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 14, 2005 |
| Grant date | Mar 13, 2007 |
| Priority date | — |
| Expiry date | Apr 14, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/518
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a manufacturing method for a recessed channel array transistor and a corresponding recessed channel array transistor. In one embodiment, the present invention uses a self-adjusting spacer on the substrate surface to provide the required distance between the gate and the source/drain regions. Thus, the requirements regarding the tolerances of the lithography in the gate contact plane are diminished.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.