Process for manufacturing vertically insulated structural components on SOI material of various thickness

US7189619B2 · kind B2 · utility

Assignee

• ATMEL Germany GmbH · DE

Inventors

• Franz Dietz · Heilbronn, DE
• Volker Dudek · Ditzingen, DE
• Michael Graf · Leutenbach, DE

Key dates

• Filing date: Jan 31, 2005
• Grant date: Mar 13, 2007
• Expiry date: May 4, 2025

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/667

Abstract

Vertically insulated active semiconductor regions having different thicknesses in an SOI wafer, which has an insulating layer, is produced. On the wafer, first active semiconductor regions having a first thickness are arranged in a layer of active semiconductor material. The second active semiconductor regions having a relatively smaller thickness are produced by epitaxial growth proceeding from at least one seed opening in a trench structure. The second semiconductor regions are substantially completely dielectrically insulated, laterally and vertically, from the first semiconductor regions by oxide layers. The width of the seed opening can be defined by lithography.