Method for reducing the contact resistance of the connection regions of a semiconductor device
US7189648B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Oct 15, 2004 |
| Grant date | Mar 13, 2007 |
| Priority date | — |
| Expiry date | Oct 15, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
One embodiment of the invention relates to a method for fabricating a semiconductor device having a semiconductor structure with a silicon region which forms at least one connection region in and/or on a surface of a substrate. The method comprises forming a metal cluster layer from a first, non-siliciding metal, followed by the deposition of a metal layer consisting of a second, siliciding metal. A subsequent heat treatment is responsible for forming a metal silicide from the second metal, the atoms of the first metal being displaced in a direction substantially perpendicular to the surface of the substrate. According to one embodiment of the invention, the atoms of the first metal are displaced by the Kirkendall effect to beneath the metal silicide. If an MOST, for example, is being fabricated, this has advantages both at the location of the source and drain region and at the location of the gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.