Bipolar transistor having reduced collector-base capacitance

US7190046B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Hiroyuki Akatsu · Yorktown Heights, US
• Rama Divakaruni · Ossining, US
• Marwan H. Khater · New York, US
• Christopher M. Schnabel · Poughkeepsie, US
• William R. Tonti · South Burlington, US

Key dates

• Filing date: Mar 29, 2004
• Grant date: Mar 13, 2007
• Expiry date: Jul 14, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/137

Abstract

Structure and method are provided for forming a bipolar transistor. As disclosed, an intrinsic base layer is provided overlying a collector layer. A low-capacitance region is disposed laterally adjacent the collector layer. The low-capacitance region includes at least one of a dielectric region and a void disposed in an undercut underlying the intrinsic base layer. An emitter layer overlies the intrinsic base layer, and a raised extrinsic base layer overlies the intrinsic base layer.