Sigma-delta analog-to-digital converter and method for reducing harmonics
US7190293B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 19, 2003 |
| Grant date | Mar 13, 2007 |
| Priority date | — |
| Expiry date | May 19, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/41
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An arrangement (100) and method for sigma-delta analog-to-digital conversion by providing parallel translating sigma-delta analog-to-digital converters (21, 22) and summing their outputs to produce a digital output signal having a bandwidth greater than that of the first or second translating sigma-delta analog-to-digital converters (21, 22). The parallel translating sigma-delta analog-to-digital converters (21, 22) use switching sequences arranged to cancel third and fifth harmonics in the digital output signal. Orthogonality error in the switching sequences applied to the sigma-delta modulators is compensated by adjusting the phase of the signals applied to mixers (51, 52).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.