CMOS imager decoder structure
US7190397B2 · kind B2 · utility
6Cited by
11References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 16, 2002 |
| Grant date | Mar 13, 2007 |
| Priority date | — |
| Expiry date | Jun 1, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/7795
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A decoder apparatus for selecting column lines of a CMOS imager pixel array is disclosed. The decoder apparatus is made up of at least one first decoder and at least one set of second decoders, each set being associated with respective first decoder. The first decoder decodes a first portion of an address representing a desired pixel array column and, depending on the results of the first decoding operation, selectively enables the associated second decoder set which decodes a second portion of the address to select a column line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.