Method of timing model abstraction for circuits containing simultaneously switching internal signals
US7191419B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 22, 2004 |
| Grant date | Mar 13, 2007 |
| Priority date | — |
| Expiry date | Dec 19, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides for determining arrival times in a circuit. An arrival time for a main signal is assigned. An arrival time for a secondary signal is assigned. It is determined whether a test is for an early arrival or for a later arrival. If the test type is for a late arrival, it is determined whether the arrival time for the secondary signal is later than for the first signal. If the test type is for an early arrival, it is determined whether the arrival time for the secondary signal is earlier than for the first signal. If the test type is for the late arrival and the arrival time for the secondary signal is later than for the first signal, assume maximum interference between the signals. If the test type is for the late arrival and the arrival time for the secondary signal is not later than for the first signal, calculate the actual interference between the signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.