Special tie-high/low cells for single metal layer route changes
US7191424B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2004 |
| Grant date | Mar 13, 2007 |
| Priority date | — |
| Expiry date | Apr 4, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/347
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for implementing a circuit design is disclosed. The method generally includes the steps of identifying, replacing and routing. The first step may identify a first cell of the circuit design having (i) a function and (ii) an input pin connectable to one of a first power rail and a second power rail having a different voltage than the first power rail. The second step may replace the first cell with a second cell having (i) the function, (ii) the input pin and (iii) at least one blocking characteristic that reserves (a) a first route completely within a particular conductive layer of the cell between the input pin and the first power rail and (b) a second route completely within the particular conductive layer between the input pin and the second power rail. The third step may route the circuit design incorporating the second cell such that the input pin is connected to one of (i) the first power rail using the first route and (ii) the second power rail using the second route.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.