Method of making a semiconductor chip assembly with simultaneously formed interconnect and connection joint
US7192803B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2003 |
| Grant date | Mar 20, 2007 |
| Priority date | — |
| Expiry date | Feb 19, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3512
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of making a semiconductor chip assembly includes providing a semiconductor chip, a metal base, an insulative base and a routing line, wherein the chip includes a conductive pad, the metal base is disposed on a side of the insulative base that faces away from the chip, and the routing line is disposed on a side of the insulative base that faces towards the chip, then etching the metal base, forming an interconnect in a via, and forming a connection joint in an opening, wherein the via extends through the insulative base, the opening extends through the insulative base, the interconnect extends through the insulative base and is electrically connected to the routing line, and the connection joint electrically connects the routing line and the pad. Preferably, the opening extends through an insulative adhesive that attaches the routing line to the chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.