Method of manufacturing semiconductor device having composite buffer layer
US7192872B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 24, 2002 |
| Grant date | Mar 20, 2007 |
| Priority date | — |
| Expiry date | Apr 30, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/157
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a method of manufacturing semiconductor device with composite buffer layers. The method includes etching grooves in n type and p type semiconductor wafers respectively. The areas of grooves in n type wafer just correspond to the areas without grooves in p type wafer, and vice versa. The grooves in both n type and p type wafers have the same depth. Two wafers are directly bonded together so that the grooves in one wafer are filled with the grooves in the other wafer. Then, chemical bonding is implemented. The bonding may also be made through thin dielectric layer (e.g. SiO2). If necessary, grinding, polishing or chemical mechanical polishing processes are carried out to remove the redundant material. Thereby, it is easy to manufacture the semiconductor device with composite buffer layer as voltage sustaining layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.