Low-K dielectric etch process for dual-damascene structures
US7192877B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 21, 2004 |
| Grant date | Mar 20, 2007 |
| Priority date | — |
| Expiry date | Oct 27, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31144
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes performing a first etch process to form a via hole in a dual-damascene integrated circuit structure comprising a first dielectric layer and a second dielectric layer. The via hole extends at least substantially through the first and second dielectric layers. The method further includes filling at least a portion of the via hole with a plug material to form a plug within the via hole, and performing a second etch process through the first dielectric layer and the portion of the plug adjacent the first dielectric layer to form a trench in the first dielectric layer. The second etch process is performed using an RF power of less than 1,000 Watts and using an etching chemistry that includes CF4 and N2. For example, second etch process may use an etching chemistry of CF4/N2/Ar, which may additionally include one or both of CO and O2.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.