Circuit structure of package substrate
US7193324B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 21, 2005 |
| Grant date | Mar 20, 2007 |
| Priority date | — |
| Expiry date | Jan 21, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/09736
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A circuit structure for a package substrate or a circuit board is provided. The circuit structure has a dielectric layer with an upper surface and a lower surface, at least a first line and at least a second line. The first line is disposed on the dielectric layer on which a base of the first line is aligned with the upper surface. In addition, the second line is disposed on the dielectric layer on which a base of the second line is embedded below the upper surface. Since the second line is embedded into the dielectric layer, the distance with a reference plane is reduced and the crosstalk between the signals is further effectively reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.