Cross-point ferroelectric memory that reduces the effects of bit line to word line shorts
US7193881B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 1, 2004 |
| Grant date | Mar 20, 2007 |
| Priority date | — |
| Expiry date | Jul 1, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory constructed from a dielectric layer sandwiched between a plurality of word conductors and a plurality of bit line conductors is disclosed. The dielectric layer includes a layer of ferroelectric material, and has first and second surfaces. The word conductors are located on the first surface. Each word conductor is connected to a corresponding word line driving circuit. The bit line conductors are located on the second surface. Each bit line conductor is connected to a corresponding bit line driving circuit and a corresponding sense amplifier by one or more disconnect switches. A disconnect switch is set to an open state if the bit line conductor connected to that disconnect switch is shorted to one of the word conductors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.