Localized cache block flush instruction
US7194587B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 24, 2003 |
| Grant date | Mar 20, 2007 |
| Priority date | — |
| Expiry date | Jun 28, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0891
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor and a related compiler support a local cache block flush instruction in which an execution unit of a processor determines an effective address. The processor forces all pending references to a cache block corresponding to the determined effective address to commit to the cache subsystem. If the referenced cache line is modified in the local cache (the cache subsystem corresponding to the processor executing the instruction), it is then written back to main memory. If the referenced block is valid in the local cache it is invalidated, but only in the local cache. If the referenced block is not valid in the local cache, there is no invalidation. Remote processors receiving a local cache block flush instruction from another processor via the system ignore the instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.