Command multiplier for built-in-self-test

US7194670B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Jonathan R. Fales · South Burlington, US
• Gregory J. Fredeman · Wappingers Falls, US
• Kevin W. Gorman · Saint Johnsbury Center, US
• Mark D. Jacunski · Colchester, US
• Toshiaki Kirihata · Poughkeepsie, US
• Alan D. Norris · South Burlington, US
• Paul C. Parries · Wappingers Falls, US
• Matthew R. Wordeman · Mahopac, US

Key dates

• Filing date: Feb 13, 2004
• Grant date: Mar 20, 2007
• Expiry date: Apr 7, 2025

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C2029/0401
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Disclosed is a flexible command multiplication scheme for the built-in-self test (BIST) of a high-speed embedded memory array that segments BIST functionality into remote lower-speed executable instructions and local higher-speed executable instructions. A stand-alone BIST logic controller operates at a lower frequency and communicates with a command multiplier using a low-speed BIST instruction seed set. The command multiplier uses offset or directive registers to drive a logic unit or ALU to generate “n” sets of CAD information which are then time-multiplexed to the embedded memory at a speed “n” times faster than the BIST operating speed.