Paul C. Parries
57Patents
11h-index
128Co-inventors
81Inventor score
Filing activity: Apr 30, 1987 → Oct 23, 2014
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US4873205A | Method for providing silicide bridge contact between silicon regions separated by a thin dielectric | Emerging Cross-Sectional Technologies | 99 | Expired |
| US5466636A | Method of forming borderless contacts using a removable mandrel | Emerging Cross-Sectional Technologies | 50 | Expired |
| US5401675A | Method of depositing conductors in high aspect ratio apertures using a collimator | Electricity | 39 | Expired |
| US4799990A | Method of self-aligning a trench isolation structure to an implanted well region | Electricity | 27 | Expired |
| US6294449A | Self-aligned contact for closely spaced transistors | Electricity | 26 | Expired |
| US7193262B2 | Low-cost deep trench decoupling capacitor device and process of manufacture | Electricity | 20 | Expired |
| US8395217B1 | Isolation in CMOSFET devices utilizing buried air bags | Electricity | 19 | Active |
| US7888723B2 | Deep trench capacitor in a SOI substrate having a laterally protruding buried strap | Electricity | 16 | Active |
| US5453400A | Method and structure for interconnecting different polysilicon zones on semiconductor substrates for integrated circuits | Electricity | 15 | Expired |
| US6967885B2 | Concurrent refresh mode with distributed row address counters in an embedded DRAM | Physics | 15 | Expired |
| US5793075A | Deep trench cell capacitor with inverting counter electrode | Electricity | 14 | Expired |
| US7923815B2 | DRAM having deep trench capacitors with lightly doped buried plates | Electricity | 10 | Active |
| US8236632B2 | FET structures with trench implantation to improve back channel leakage and body resistance | Electricity | 9 | Active |
| US5672901A | Structure for interconnecting different polysilicon zones on semiconductor substrates for integrated circuits | Electricity | 9 | Expired |
| US6410399B1 | Process to lower strap, wordline and bitline contact resistance in trench-based DRAMS by silicidization | Electricity | 9 | Expired |
| US5976982A | Methods for protecting device components from chemical mechanical polish induced defects | Electricity | 8 | Expired |
| US6194736A | Quantum conductive recrystallization barrier layers | Electricity | 8 | Expired |
| US6518145B1 | Methods to control the threshold voltage of a deep trench corner device | Electricity | 7 | Expired |
| US7078756B2 | Collarless trench DRAM device | Electricity | 7 | Expired |
| US7194670B2 | Command multiplier for built-in-self-test | Physics | 6 | Expired |
| US6265278A | Deep trench cell capacitor with inverting counter electrode | Electricity | 6 | Expired |
| US8273629B2 | Through-gate implant for body dopant | Electricity | 6 | Active |
| US7791124B2 | SOI deep trench capacitor employing a non-conformal inner spacer | Electricity | 5 | Active |
| US7705386B2 | Providing isolation for wordline passing over deep trench capacitor | Electricity | 5 | Active |
| US8809953B2 | FET structures with trench implantation to improve back channel leakage and body resistance | Electricity | 5 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.