Method and apparatus for identifying line-end features for lithography verification
US7194712B2 · kind B2 · utility
191Cited by
2References
24Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 12, 2004 |
| Grant date | Mar 20, 2007 |
| Priority date | — |
| Expiry date | Jun 21, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One embodiment of the invention provides a system that facilitates identifying line-end features in a layout for an integrated circuit. The system operates by first receiving the layout for the integrated circuit. Next, the system selects a polygon from the layout and marks a line-end seed on the polygon. The system then determines if the line-end seed is associated with a line feature, and if so, the system marks the line-end feature inside the line feature.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.