Trench capacitor DRAM cell using buried oxide as array top oxide

US7195972B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Dureseti Chidambarrao · Weston, US
• Ramachandra Divakaruni · Ossining, US
• Deok-kee Kim · Mount Kisco, US

Key dates

• Filing date: Jul 6, 2004
• Grant date: Mar 27, 2007
• Expiry date: Aug 1, 2025

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/201

Abstract

A trench capacitor DRAM cell in an SOI wafer uses the silicon device layer in the array as part of passing wordlines, stripping the silicon device layer in the array outside the wordlines and uses the BOX layer as the array top oxide separating the passing wordlines from the substrate.